1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of diodes in integrated circuits that may be used for ESD (electrostatic discharge) protection, temperature monitoring and the like.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, a huge number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been accomplished over the recent decades regarding the performance and the feature size of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. A promising design alternative for high-end integrated circuits having reduced parasitic capacitance and thus the potential for obtaining higher operating speeds represent so-called SOI (silicon on insulator) devices, which are fabricated within and on a thin crystalline silicon layer provided on an insulating substrate. Recently, SOI substrates having formed thereon a crystalline silicon layer of a comparable quality to that of bulk silicon substrates are now available at reasonable costs and render high-end circuits, such as microprocessors and the like, as attractive candidates for being fabricated on SOI substrates.
Although SOI devices offer a plurality of advantages due to the fact that the circuit elements may entirely be insulated from adjacent circuit elements, additional problems not encountered with devices fabricated on bulk silicon (bulk devices) may arise or other problems also addressed in bulk devices may even be exaggerated in SOI devices. For instance, the well region of a transistor device is typically isolated and the potential thereof floats, wherein, for example, minority charge carriers may accumulate and adversely influence the transistor characteristics, such as the threshold voltage. Thus, certain counter-measures, such as additional substrate contacts, band gap engineering, and the like, have to be taken so as to obtain the desired transistor performance. Moreover, the heat conductivity in SOI devices may usually be significantly lower than in bulk devices due to the low heat conductivity of the insulating layer that separates the semiconductor layer accommodating a circuit element and the substrate. Therefore, substantially all of the heat created in the semi-conductor layer has to be dissipated by the electric connections. The problem of heat dissipation becomes even more relevant in modem integrated circuits, which are typically operated at high clock frequencies and have an extremely high package density that continues to increase with every new circuit generation. Additionally, in SOI CMOS devices, the risk of damaging circuit elements by electrostatic discharge still exists in the same way as in bulk devices. Therefore, effective diode structures for discharging the excess charges are required, wherein the entire current and the heat associated therewith has to be conducted by the doped regions and the electric contacts connected thereto. Since relatively high currents may have to be discharged, a remarkable amount of additional heat may be created.
It is therefore very important to provide diode structures in SOI devices that exhibit characteristics approaching as closely as possible the characteristics of an ideal diode, thereby allowing effective monitoring of the die internal temperature and/or protection of the circuitry upon occurrence of ESD events.
With reference to FIG. 1, a conventional silicon diode structure as used in SOI devices will now be described in more detail to illustrate some of the problems associated therewith. In FIG. 1, a semiconductor structure 100 comprises a substrate 101, for example, a silicon substrate, having formed thereon an insulating layer 102 that is commonly referred to as a buried oxide layer, since, frequently, the insulating layer 102 is comprised of silicon dioxide. A semiconductor layer 103 is formed on the insulating layer 102 and comprises isolation trenches 104 that enclose an active region 105. The active region 105 may include dopants, such as P-type dopants in the form of boron. A highly doped P-type region 106 and a highly doped N-type region 107 are formed in the active region 105, wherein the highly doped N-type region 107, together with the P-doped active region 105, form a PN-junction 108. A thin insulating layer 109, which will be referred to as a gate insulation layer, is formed on the active region 105 and separates a conductive line 110, such as a polysilicon line, from the active region 105. The P-type region 106, the N-type region 107 and the polysilicon line 110 comprise silicide regions 111 including a silicide of any appropriate refractory metal, such as cobalt, nickel, titanium and the like. Moreover, sidewall spacers 112 are formed on sidewalls of the polysilicon line 110. In principle, the circuit element described so far may be considered as a typical transistor structure with the exception of the highly doped regions 106 and 107, which are doped inversely to each other, contrary to a regular N-channel MOS transistor that would comprise two highly doped N-type regions. Due to the similarity to an ordinary MOS transistor structure, the polysilicon line 110 will also be referred to as gate electrode 110.
The semiconductor structure 100 further comprises contact plugs 113 and 114 including, for example, tungsten and possibly any appropriate barrier layer (not shown), to provide enhanced diffusion barrier characteristics and adhesion to a surrounding insulating layer 115 that may, for example, be comprised of silicon dioxide. The contact plugs 113 and 114 may be connected to corresponding metal regions or metal lines 116 and 117, wherein the contact plug 114 is additionally connected to the gate electrode 110, for example in the form of a local interconnect (not shown). The metal lines 116, 117 are to represent one or more metallization layers required to provide the electrical connection to other circuit elements or to peripheral devices.
A typical process flow for manufacturing the semiconductor structure 100 may comprise the following processes. The substrate 101 including the insulating layer 102 and the semiconductor layer 103 may be formed by well-known wafer bonding techniques that provide the semiconductor layer 103 with a quality of the crystalline structure identical to that of bulk substrates. Thereafter, the isolation structures 104 may be formed by well-established photolithography, deposition and etch techniques. Thereafter, the gate insulation layer 109 and the gate electrode 110 may be formed in conformity with the typical process flow for the formation of transistor structures, which may simultaneously be provided at other areas of the substrate 101. The lateral dimension of the gate electrode 110 may be adjusted in accordance with design requirements in such a manner that an appropriate implantation mask is provided for subsequent implantation steps.
Prior to the formation of the gate electrode 110, one or more implantation steps may be carried out so as to provide a desired dopant profile in the active region 105. Thereafter, the gate electrode 110 is formed by patterning a polysilicon layer (not shown) using well-established photolithography and etch techniques. Next, a further implantation step may be performed to create, for example, the N-type region 107, wherein the part of the active region 105 intended to receive the region 106 is covered by a corresponding resist mask (not shown). Thereafter, the resist mask may be removed, a further resist mask may be formed over the N-type region 107, and a further implantation sequence may be performed to create the P-type region 106. During the implantation processes for forming the regions 106, 107, the corresponding resist masks may substantially avoid dopant penetration in the respective covered region, whereas it is, however, the gate electrode 110 that provides for the precise adjustment of the dopant profile of the regions 106, 107 below the gate insulation layer 109. Therefore, the gate electrode 110 substantially determines the characteristics, i.e., the dopant concentration, of the PN-junction 108. Typically, the implantation sequences are performed under conditions and with process parameters as required for the simultaneous formation of other transistor devices. Therefore, the implantation sequence may also include any sophisticated implantation techniques, such as tilted implantations and a halo implantation, as is usually necessary for high-end transistor structures. Although these implantation techniques may provide significant advantages for the transistor structures, the characteristic of the PN-junction 108, which substantially determines the diode behavior of the semiconductor structure 100, may remarkably deviate from the ideal diode characteristic. Moreover, any short channel effects as well as the floating body effect may necessitate additional complex dopant profiles within the active region 105, which may further adversely affect the electrical characteristics of the semiconductor structure 100.
Thereafter, the sidewall spacers 112 may be formed by depositing an insulating material and anistropically etching the dielectric material. Next, a refractory metal layer may be formed over the structure 100 and a heat treatment may be carried out so as to form the silicide regions 111 in the regions 106, 107 and the gate electrode 110. Thereafter, the dielectric layer 115 is formed by any appropriate deposition method and the contact plugs 113 and 114 are formed by etching respective vias into the dielectric layer 115 and filling the same with an appropriate barrier metal and a contact metal. During the formation of the contact plugs 113, 114, an electrical connection (not shown) to the gate electrode 110 is also formed to obtain a defined potential at the gate electrode 110 during the operation of the semiconductor structure 100. Finally, one or more metallization layers are formed, represented by the metal regions and lines 116, 117, so as to provide for the required electrical connections to other circuit elements and/or the periphery.
During operation of the semiconductor structure 100, which acts as a diode, the region 106, acting as an anode, and the region 107, acting as a cathode, of the diode structure are electrically connected in conformity with the circuit layout under consideration. For instance, a voltage supplied to the regions 106 and 107 may create a current through the PN-junction 108, wherein the current substantially depends exponentially on the applied voltage and temperature. Depending on the “ideality” of the PN-junction 108, the temperature may be monitored more or less accurately. As previously noted, tilted halo implantations as well as further advanced implantation schemes to control the floating body effect may have a significant influence on the diode characteristic. Moreover, the continual scaling of semiconductor devices also requires a corresponding reduction of the thickness of the semiconductor layer 103. The MOS structure, that is, the conductive gate electrode 110, the gate insulation layer 109 and the underlying active region 105, may cause a depletion region in the active region 105, which also influences the behavior of the PN-junction 108. A corresponding ratio between a depleted region below the gate insulation layer 109 and a quasi-neutral region, which is the main factor determining the diode behavior of the PN-junction 108, usually depends on the thickness of the layer 103. Consequently, an ongoing reduction of the thickness of the layer 103 as required for scaling SOI devices may increasingly adversely influence the diode characteristics of the structure 100. In extreme cases, the active region 105 may be depleted entirely, resulting in a substantially complete elimination of the diode function of the structure 100. Hence, a further scaling of SOI devices may suffer from a reduced ideality of integrated diode structures.
In view of the problems identified above, a need exists for an improved technique for forming diode structures on an SOI substrate, which provides enhanced diode characteristics for scaled SOI devices.